Output, tri state, active low. Indicates that the address ( A0 - A15) bus holds a valid address for an I/O operation.

Output, tri-state, active low. Indicates that the CPU wants to read data from memory or from an I/O device.

Output, tri-state, active low. Indicates that the CPU data bus holds valid data to be written to memory or an I/O device.

Output, active low. Indicates that the lower seven bits of the address bus contain a refresh address for dynamic memories. A concurrent MREQ signal should then be used to signal a refresh read to all dynamic memories in the system.

Output, active low. Indicates that the CPU has executed a HALT software instruction and is awaiting either a non-maskable or maskable interrupt (with the mask enabled) before normal operation can be resumed. (Memory refresh continues in the HALT state with the CPU executing a NOP instruction.)

Input, active low. An interrupt request generated by external devices will be honoured at the end of the current instruction if the internal (software controlled) interrupt enable flip-flop (IFF) is enabled and if the BUSRQ signal is not active. When the CPU accepts the interrupt an acknowledge signal is generated (IORQ) at the beginning (Ml cycle) of the next instruction.

Input, negative edge triggered. The non-maskable interrupt line has a higher priority than INT and is always recognized at the end of the current instruction independent of the state of the IFF. NMI forces the CPU to restart at location 0066H. The PC contents are automatically saved on the stack to facilitate an orderly return to the program.

Input, active low. Forces the PC to zero and initialises the CPU such that the IFF is reset (interrupts disabled), registers I and R are set to OOH, and interrupt mode 0 is enabled. During reset periods, the address and data buses go to a high impedance state and all output signals become inactive.

Input, active low. Used by external devices as a signal to the CPU when they wish to have control of the system buses. At the end of the current machine cycle in which the signal is received the CPU will set all tri-state lines to the high impedance state.

Output, active low. Used by the CPU to signal to external devices that the system buses are in the high impedance state and available for their use.

  The Z80A CPU contains 18 8-bit and four 16-bit registers, jointly constituting a total of 208 bits of read/write memory accessible to the programmer. The register configuration of the Z80A CPU is shown in below.

  Note that this shows two sets of six general purpose registers which may be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag registers. The functions of the registers are summarized here;

Two independent registers each capable of holding a 16-bit offset address used in the indexed addressing mode.

One of the Z80A interrupt modes allows an indirect call to an address located anywhere in memory (i.e. not just zero page). The I register is used to hold the high order eight bits of this address.

The R register contains the output of a 7-bit refresh counter. The count is incremented after each instruction fetch. The contents of the R register are sent to the lower eight bits of the address bus during the refresh period.

Internal block diagram of the Z80A core.

This is what it all looks like.